Why use cpld

Programming kept on power down CPLD functions available instantly on system power up Almost impossible to steal stored design Improves security, simplifies design. Designing with CPLDs.

Choosing a CPLD. Performance Xilinx CPLDs come in a variety of speed grades so that you only pay for the performance you need. Choosing a software package. Implementing a design. Implementation includes: Design entry Programming and testing the prototype Documentation. The use of combinatorial logic function supports wide fan-in. This means FPGAs can be specialized for more complex computation and applications. CPLDs are programmable using an electrically erasable programmable read-only memory EEPROM , so their configuration is stored in non-volatile memory and can be accessed even after a reboot.

However, major chip makers are designing the next generation of FPGAs to have non-volatile memory, eliminating the need for an external module. The reconfigurable nature and complicated architecture of an FPGA makes their signal processing delay unpredictable. Simply counting the number of operations executed within your FPGA is not sufficient for predicting delay.

In contrast, CPLDs have much lower pin-to-pin delay for the same switching frequency due to their simpler architecture. This is quite important to consider if you need to synchronize parallel data across different signal nets. Older CPLDs families consumed enough power to make them prohibitive in applications requiring battery power. In comparison, an FPGA running at full clock speed and switching at high frequency requires some level of thermal management; such as a passive heat sink or more intensive active methods, like using a fan or even an evaporative heat exchanger.

These chips are inadequate to fairly modest sizes, normally supporting a mutual number of inputs and outputs of not more than A CPLD chip includes several circuit blocks on a single chip with inside wiring resources to attach the circuit blocks.

These can handle knowingly higher designs than SPLDs simple programmable logic devices , but offer less logic than FPGAs field programmable gate arrays. CPLDs include numerous logic blocks; each of the blocks includes macrocells. Because every logic block executes a specific function, all of the macrocells in a logic block are fully connected.

Depending upon the use, these blocks may or may not be connected to one another. Most CPLDs complex programmable logic devices have macrocells with a sum of logic function and an elective FF flip-flop. The time delay can be as large as several tens of milliseconds. CPLDs remain programmed, and retain their circuit after powering down. FPGAs go blank as soon as powered-off. The contents of the memory is lost as soon as power is disconnected. Deterministic Timing Analysis. This opens up the possibility less deterministic signal routing and thus causing complicated timing scenarios.

Thankfully implementation tools provided by FPGA vendors have mechanisms to assist achieving deterministic timing. But additional steps by the user is usually necessary to achieve this. Lower idle power consumption.